- Module is a built-in Chisel class that all hardware modules must extend.
- THe io'e are defined using a special val io. must of of the IO object/instance
- Bundle - Hardware struct type
- := operator is a Chisel operator that indicates that the right-hand signal drives the left-hand signal. It is a directioned operator.
- Elaboration : we then use Scala to call the Chisel compiler to translate Chisel Passthrough into Verilog Passthrough. getVerilog(new Passthrough))
- Parameterization Chisel module is implemented as a Scala class. Just like any other Scala class, we could make a Chisel module take some construction parameters. Powerful parameterization. parameterization is enabled by Scala, not Chisel; Chisel has no extra APIs for parameterization, but a designer can simply leverage Scala features to parameterize his/her designs.
- Chisel test harness
- poke
- expect
val testResult = Driver(() => new Passthrough()) {
c => new PeekPokeTester(c) {
poke(c.io.in, 0) // Set our input to value 0
expect(c.io.out, 0) // Assert that the output correctly has 0
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- Chisel printf has its own string interpolator too
printf(p"Print during simulation: IO is $io\n")
- printf vs println in scala
Combinatorial circuits
- Basic chisel types - SInt, UInt, and bool
- During hardware construction, use val only not var since the construct itself never changes, only the value it holds druing simulation changes
- We've called our class MyModule, and it extends Module. This means it gets mapped to a hardware module in Verilog.
- [QUESTION] Is there something like a synthesizable subset?? what does it mean that everything within a class tht extends Module is synthesizable
- {QUESTION} Does firrtl/verilog capture entire information about design i.e. no information loss?
- {QUESTION} : datatype of priting 1.U + 1.U in exercise UInt<1>(OpResult in MyModule). This is seen as a Hardware node, and not as an addition of 1 + 1
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